1. Field of the Invention
The present invention generally relates to a method for forming a recess gate of a semiconductor device, and more specifically, to a method for forming a recess gate of a semiconductor device wherein a contact region is formed by depositing a polysilicon layer pattern covering the contact region prior to the formations of a recess gate region and a gate structure to suppress increase in resistance of the contact region and tWR (Write Recovery time) characteristics.
2. Description of the Related Art
FIG. 1 is a cross-sectional view illustrating a conventional method for forming a recess gate of a semiconductor device.
Referring to FIG. 1, a predetermined region of a semiconductor substrate 10 where a channel region is to be formed is etched to form a recess gate region (not shown). Thereafter, a gate oxide film (not shown) is formed in the recess gate region.
Next, a planarized polysilicon layer (not shown) filling up the recess gate region is formed on the entire surface. A stacked structure of a gate conductive layer and a gate hard mask layer is then formed on the planarized polysilicon layer.
Afterward, the stacked structure and the polysilicon layer are patterned to form a gate structure including a polysilicon layer pattern 30, a gate conductive layer pattern 40 and a gate hard mask layer pattern 50. Thereafter, a spacer 60 is formed on a sidewall of the gate structure.
In accordance with the above-described conventional method for forming a recess gate of a semiconductor device, when misalignment between a device isolation film and the gate structure occurs resistance of a storage node contact region of one cell of the two sharing one active region occurs due to overlay.
Moreover, the misalignment between the device isolation film and the gate structure causes the storage contact region to be not completely exposed in a subsequent etching process for forming a landing plug contact hole. As a result, the tWR characteristic of the device is deteriorated.